This chapter documents the Backend for the c16x/st10 microcontroller
family.

   Note that this module is not yet fully completed!

1 Legal
=======

This module is written in 2002-2004 by Volker Barthelmann and is covered
by the vasm copyright without modifications.

2 Additional options for this module
====================================

This module provides the following additional options:

'-no-translations'
     Do not translate between jump instructions.  If the offset of a
     'jmpr' instruction is too large, it will not be translated to
     'jmps' but an error will be emitted.

     Also, 'jmpa' will not be optimized to 'jmpr'.

     The pseudo-instruction 'jmp' will still be translated.

'-jmpa'
     A 'jmp' or 'jmpr' instruction that is translated due to its offset
     being larger than 8 bits will be translated to a 'jmpa' rather than
     a 'jmps', if possible.

3 General
=========

This backend accepts c16x/st10 instructions as described in the Infineon
instruction set manuals.

   The target address type is 32bit.

   Default alignment for sections and instructions is 2 bytes.

4 Extensions
============

This backend provides the following specific extensions:

   - There is a pseudo instruction 'jmp' that will be translated either
     to a 'jmpr' or 'jmpa' instruction, depending on the offset.

   - The 'sfr' pseudo opcode can be used to declare special function
     registers.  It has two, three of four arguments.  The first
     argument is the identifier to be declared as special function
     register.  The second argument is either the 16bit sfr address or
     its 8bit base address (0xfe for normal sfrs and 0xf0 for extended
     special function registers).  In the latter case, the third
     argument is the 8bit sfr number.  If another argument is given, it
     specifies the bit-number in the sfr (i.e.  the declaration declares
     a single bit).

     Example:
          .sfr    zeros,0xfe,0x8e

   - 'SEG' and 'SOF' can be used to obtain the segment or segment offset
     of a full address.  Example:
                  mov r3,#SEG farfunc

5 Optimizations
===============

This backend performs the following optimizations:

   - 'jmp' is translated to 'jmpr', if possible.  Also, if
     '-no-translations' was not specified, 'jmpr' and 'jmpa' are
     translated.

   - Relative jump instructions with an offset that does not fit into 8
     bits are translated to a 'jmps' instruction or an inverted jump
     around a 'jmps' instruction.

   - For instruction that have two forms 'gpr,#IMM3/4' and 'reg,#IMM16'
     the smaller form is used, if possible.

6 Known Problems
================

Some known problems of this module at the moment:

   - Lots...

7 Error Messages
================

This module has the following error messages:

   - 2001: illegal operand
   - 2002: word register expected
   - 2004: value does not find in %d bits
   - 2005: data size not supported
   - 2006: illegal use of SOF
   - 2007: illegal use of SEG
   - 2008: illegal use of DPP prefix
